SHA1 Verilog code. 8bit interfaces

Xilinx XC2VP20 FPGAs. The complete SHA-1 chip Verilog source

利用verilog语言实现了SHA-1机密算法，具体算法与加密芯片ds28e01一致。-Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.