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vhdl平方根
- 计算某数的平方根，VHDL语言，使用简单-calculate the square root of a number, VHDL, use simple
ddfs
- 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
wave_genarator_vhdl
- vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control
arith_lib_cadence
- Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
pre_norm_sqrt
- 一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
sqrt
- This zip file contains the verilog source code for square root calculation and its test bench
SIGNAL_GEN
- 利用EDA的VHDL硬件描述语言设计的函数信号发生器，可以产生递增、递减斜波，三角波，阶梯波，正弦波，方波-The use of EDA, VHDL hardware descr iption language design function of the signal generator can generate increased progressively decreasing ramp, triangle wave, step-wave, sine wave, square wave
square-root
- Verilog硬件描述语言能够用软件语言的的方式描述硬件特性，并可用仿真方式完成电路的调试.本文介绍了基于EasyFPGA030的开平方运算器的设计，详细说明了运用verilog语言的设计过程与实现成果。-Verilog hardware descr iption language（HDL）specializes in describing hardware in the way of software language, and complete circuit simulation avai
square
- This a verilog code for the generation of a square wave-This is a verilog code for the generation of a square wave..
S6_VGA_change
- 程序可以在VGA显示器上以800x600分辨率显示方波示例和字母示例-Program can display in VGA resolution display with 800x600 square wave sample and sample letters
HDLImplementationoftheVariableStepSize
- proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithm
wave_finish
- 基于quartus2的信号发生器，可产生正弦，三角，方波-Based quartus2 signal generator can produce sine, triangle, square wave. .
LinPF_RLS
- VHDL code for linear prediction filter based on RLS (recursive least square). Filter order is set to 4, bit precision set to 12 bits for input and output. Signals are complex signals.
sqrt_for_single_float_point
- 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
square
- Move square on monitor and change color with FPGA
A-VHDL-Function-for-finding-SQUARE-ROOT
- vhdl coding for square root-vhdl coding for square root...
square-generator
- 本文描述了怎样进行方波信号的产生，步骤，还有相关的程序-this paper describe how to generate square wave
33-square-root
- 使用VHDL语言实现33位平方根进位选择加法器，能满足在500M时钟下正确工作，使用DB测试，并通过前仿。-Using VHDL language 33 square root carry select adder, to meet in the 500M clock work correctly, use the DB test, and through imitation.
Square-wave-generator
- 能过通过PC上的串口发送数据去控制FPGA引脚输出方波的频率，占空比！-This program can be had through the serial port on the PC to send data to the control FPGA pin output square wave frequency, duty cycle!
Square-Root
- Square Root code in VHDL