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uvm
- the Universal Verification Methodology (UVM) for creating SystemVerilog testbenches.
uvm-1.1d.tar
- UVM World 官方发布的UVM(通用验证方法学)的源代码,基于SystemVerilog,用于ASIC Verification。2013-03最新发布版本uvm-1.1d.tar.gz-The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03
uart2bus_testbench_latest.tar
- uart2bus_testbench,uart测试平台,主要运用uvm验证方法学,对uart接口、systemverilog和uvm等ic开发和验证有一个初步了解和掌握。-Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic development and verification have a pre
AHB2-master
- AMBA AHB 2.0 VIP in SystemVerilog UVM
AHB5-master
- amba ahb2 协议vip,包括master和slave(AMBA AHB 2.0 VIP in SystemVerilog UVM)