搜索资源列表
cronometro
- This the program of a timer with a accuracy of ms-This is the program of a timer with a accuracy of ms
shuzizhong2008
- 这时一个关于数字钟的VHDL程序，有计时、校时、报时等功能-When a digital clock on the VHDL program, there is time, school time, timer and other functions
counter
- 用VHDL语言实现的计时器，最大计时为24小时，计时精度为1ms，设有复位和暂停功能，使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz.
VHDL_32bit_timer
- VHDL写的32位计数，两个四位共阳数码管输出 串口输出+数码管显示的计时器程序 每次停止后串口输出。-VHDL to write 32-bit count, a total of two 4-yang control output serial digital output+ digital tube displays each stopped the timer program serial output.
sopc_timer
- sopc的一个典型应用，使用的部件为niosII软核中的timer定时器，内容详细，包括所有的源代码。-sopc a typical application, the use of soft-core components of niosII timer in the timer and detailed, including all the source code.
niosII
- 很好地描述了NOISII的串口、定时中断等各种实例-A good descr iption of the NOISII the serial port, timer interrupt, and other examples of
divider
- 用VHDL实现了一个计时器，在SPANTAN3E上验证通过-VHDL, implements a timer, in the SPANTAN3E verified by the
timer
- 基于VHDL语言，实现时钟功能，显示时间从00：00：00到23：59：59，并将其输出信号转换为数码管信号-Based on the VHDL language, to achieve the clock function, display time from 00:00:00 to 23:59:59, and the output signal is converted to digital control signals
clock
- FPGA用lcd显示屏实现的24小时的计时器-FPGA with the lcd screen to achieve a 24-hour timer
timer
- 这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。-This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, t
traffic
- 基于DE2平台VHDL下编程，交通灯及计时器控制实验程序-Under the DE2 platform based on VHDL programming, traffic lights and timer control of experimental procedure
DF2C8_02_Key_SW_LED
- 1：按下复位按键，四个 LED 熄灭 2：如果拨码开关全部为 OFF 状态（输入 1111） ，四个 LED 从左到右依次点亮（跑马灯 效果） ，周而复始； 3：如果拨码开关不全为 OFF 状态（输入 0000~1110） ，四个 LED从左到右依次点亮（跑 马灯效果） ，周而复始； 4：如果按下四个轻触按键中的任意一个，LED 将全部点亮，放开按键后 LED 将恢复到 左移或右移操作，但移位操作的计
timer1
- 3 digit 7-segment display timer using VHDL.
maichongbbbb
- 学习利用集成逻辑门、555定时器设计脉冲信号产生电路；掌握影响脉冲波形参数的定时元件参数的计算方法；学习脉冲波形整形和分频方法 -Learning to use the integrated logic gate, 555 timer pulse signal generation circuit design control parameters affect the timing pulse device parameters is calculated study pulse sh
7
- 调用总共四个计数器（两个六进制，两个十进制，六进制计数器可由实验五的程序做简单修改而成）串起来构成异步计数器，计数器的值，通过实验九串行扫描输出。用1Hz连续脉冲作为输入，这样就构成一个简单的1h计时器。带一个清零端。 输入：连续脉冲，逻辑开关；输出：七段LED。 -Called a total of four counters (two six-band, two decimal, hexadecimal counter by six experimental procedure
TIMER
- 这个为倒计时时钟显示控制实验例子程序，大家可以参考-The countdown clock shows control experiments for the example program, we can refer to
DIP_0034_timer_amba
- This Good-Timer Program-This is Good-Timer Program
dingshiqi188
- VHDL--定时器设计-Design of a Timer Based on CPLD
MyPWM
- 基于FPGA ALTERA EP2C5Q8208C8，自制PWM控制器，配合上位机定时器-based on FPGA ALTERA EP2C5Q，PWM controller,with MCU TIMER
FPGA
- fpga时延与定时控制,描述了设计时的注意事项-FPGA time delay and timer control