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USB 2.0 IP Core
- USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
FPGA-digital-circuit-design
- < FPGA数字电子系统设计与开发实例导航> 一书的代码，FPGA数字电子系统设计与开发实例导航,用硬件描述语言编写的，I2C,UART,USB，VGA，CAN-BUS，网络等等的书籍配套原代码。。。。 使用方法： 1.拷贝到硬盘。 2.用ISE创建项目，分别加入各个代码文件，即可。
FT245_R_W
- USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.
usb_funct.tar
- Verilog语言描述的USB 2.0接口和新功能固件。
FPGACPLD
- FPGA数字电子系统设计与开发实例导航> 一书的代码，FPGA数字电子系统设计与开发实例导航,用硬件描述语言编写的，I2C,UART,USB，VGA，CAN-BUS，网络等等的书籍配套原代码。。。。使用方法： 1.拷贝到硬盘。 2.用ISE创建项目，分别加入各个代码文件，即可
usb_latest.tar
- 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
FT2232H_USB_Core
- 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieve
Oscilloscope
- The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware.
USB20_FPGA_imagegather
- FPGA实现USB2.0图像采集，包括软硬件设计-fpga for usb 2.0 image gather，include software and hardware design
The-USB-2.0-Physical-Layer_-Standard-and-Implemen
- THIS DOCUMENT IS USB 2.0 PHYSICAL LAYER STANDARD AND IMPLEMENTATION BY GERRIT W DEN BESTON ...VERY USEFUL WHILE IAM DOING PHYSICAL LAYER IMPLEMNTATION OF USB
EMP240USB
- 1、电路图-----AD6.7 2、CPLD-------QUARTUS7.0 3、运行CDM_Setup.exe安装FT245的驱动程序 4、插上USB线，电路上电后，会提示自动安装驱动程序，如果安装成功，可以在设备管理器中看到Altera USB-Blaster 4、运行MProg3.0_Setup.exe，将altera.ept文件烧入FT245RL的内部EEPROM（FT245BM是在外部94LC46中） 5、打开QUARTUS，就可以在下载器中发现USB-0（
usb1_funct_latest.tar
- USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi
com8001matlab_cpp_007
- zip file for usb 2.0 interfacing with fpga
USB-2.0-source-code-by-VHDL
- 实现USB2.0，采用VHDL编写，源代码已按类分好-USB 2.0 source code by VHDL
cy7c68013_Keyboard
- cy7c68013 USB2.0芯片 键盘控制设计源代码-CY7C68013 USB 2.0 chip keyboard to control the design of the source code
USB2.0-IP
- USB2.0 IP核源代码，经典好用！写这么多真没意思！-USB 2.0 IP core source code, easy to use classic! Write so really boring!
CycloneIII_EP3C40F780C8_25_USB2_Test
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,USB 2.0 c测试实验代码 -SOPC,CycloneIII，EP3C40F780C8，NIOS II IDE, USB2.0 code
Codes
- USB 2.0 using VHDL with files : main.c, drice.c and HIGH_SPEED_USB_CORE_SETUP_TRANSACTION
fpga_usb_serial_20111004.tar
- usb 2.0 functional code
utsya
- Constituting the modulated signals of different frequencies, Channelized receiver based on multi-phase structure, Rotating machinery 2-d holographic spectrum calculation.