搜索资源列表
uvm-1.0p1.tar
- Cadence 公司推出的高级验证语言，验证方法学开源-Cadence s introduction of an advanced verification languages, verification methodology open source
uvm-1.1d.tar
- UVM World 官方发布的UVM（通用验证方法学）的源代码，基于SystemVerilog，用于ASIC Verification。2013-03最新发布版本uvm-1.1d.tar.gz-The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03
uvm_switch_8
- 使用uvm验证环境搭建的testbench，主要验证switch的功能。可以学习uvm的简单功能-use uvm set up testbench ,the mainly focuse is verification swtich,you can learning uvm sample fucntion
uvm-1.1
- 学习IC验证的好资料，包括UVM-1.1a和UVM-1.1d的全部工程example,适合IC验证基于UVM平台的初学者。-Learn good about IC verification, including all engineering of UVM-1.1a and UVM-1.1d, for beginners based on the UVM platform for IC verification.
uart2bus_testbench_latest.tar
- uart2bus_testbench,uart测试平台，主要运用uvm验证方法学，对uart接口、systemverilog和uvm等ic开发和验证有一个初步了解和掌握。-Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic development and verification have a pre
crc7
- 以crc7为例进行UVM的验证 Part 1： 搭建环境。 本文使用的Quartus II 13.1（64 bit），器件库MAX V。写了一个Verilog的简单的crc7。 仿真环境是ModelSim 10.2c。虽说自带UVM库。但是，没找到Modelsim自带的uvm_dpi.dll，于是，还重新编译了一番。 本文在win 10下。下载uvm-1.1d（现在最新版本有1.2d了），放好。(crc7 code by system verilog language)
UVM验证平台搭建
- 搭建uvm验证平台,通用验证平台结构和搭建流程介绍(How to build a common UVM verification platform?An easy and useful method is instroduced here.)
SPI_UVM_VIP
- SPI协议的芯片验证VIP,用UVM搭建平台验证代码(Chip verification VIP of SPI protocol, build platform verification code with UVM)
01_router_lab_all
- 基于UVM平台搭建的验证环境，针对的是路由器router模块，可供参考(The verification environment based on UVM platform aims at router module of router, which can be used for reference)
基于ahb总线的sramc设计与验证（SV，uvm）
- 基于ahb总线的sramc设计与验证（E课网）