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systemcTOVerlogHDL
- 一个带波形输出的扫频模板systemC源程序， 该程序在SystemCStudio开发平台下生成， 实现systemC仿真、波形显示以及自动生成Verilog HDL代码。-waveform output with a sweep of the template systemC source, SystemCStudio the program development platform in the next generation, realize systemC simulation,
xge_mac
- 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below.
A_SystemC_Primer
- 本书籍主要讲的是SYSTEMC也是一种硬件描述语言，此语言跟VERILOG和VHDL相比很多优点，尤其是在写测试代码方面。一共三本，希望对大家有帮助。-This book is mainly about SYSTEMC is also a hardware descr iption language, this language VERILOG and VHDL, compared with many advantages, particularly in the area to write t
catapult_sc_user
- 非常好的Mentor catapult学习书, catabult 可用于高级综合，由c产生vhdl/verilog。 这本与systemC相关。-very nice book for catabult study
Axi_mux
- The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the lib
System_Demons
- 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实
vertosysc
- verilog转换为systemc代码,用于RTL到系统建模-verilog to systemc
mips_8bit
- Multicycle MIPS implementation in SystemC Systemc is C based for Hardware Descr iption (similar to verilog/vhdl)