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vhdl-devider
- 基于vhdl的分频器设计，分频器在数字系统设计中应用频繁-VHDL-based design of the divider, divider in the digital system design applications frequently
clk_div
- Clock devider in VHDL code
debouncer_vhdl
- debouncer in vhdl with clock devider parameter and number of inputs