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DES.zip
- DES 加密算法的实现,使用硬件描述语言VHDL编写,DES encryption algorithm realization, uses hardware descr iption language VHDL to compile
Chapter10
- 第十章的代码。 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
aes
- verilog实现的AES-128加解密程序,FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
rc5_enc
- rc5的encryption,带state machine,一共四种状态st_idle,st_ready,st_round_op,st_pre_round-RC5 of encryption, with state machine, a total of four state st_idle, st_ready, st_round_op, st_pre_round
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
rc4
- RC4算法,WEP算法,加解密,密钥长度256-RC4 algorithm, WEP algorithm, encryption and decryption
OPERATION_UNIT
- 本程序为加密芯片内部加密运算单元部分,包括32位减法器、移位寄存器、加/减法器、寄存器等,对密码芯片运算部分设计具有一定指导意义-The procedure for encryption chip unit internal encryption algorithms, including 32-bit subtraction, and shift register, add/subtraction, and register and so on password-chip design has
DES101
- 数据加密算法(Data Encryption Algorithm,DEA)的数据加密标准(Data Encryption Standard,DES)是规范的描述,它出自 IBM 的研究工作,并在 1997 年被美国政府正式采纳。它很可能是使用最广泛的秘钥系统,特别是在保护金融数据的安全中,最初开发的 DES 是嵌入硬 件中的。通常,自动取款机(Automated Teller Machine,ATM)都使用 DES。文件是DES代码的VHDL描述 -Data encryption algor
rc5spartanboard
- rc5 encryption implementation using vhdl on spartan board-rc5 encryption implementation using vhdl on spartan board...
ideacore1
- This is IDEA encryption Algorithm. Tested on Sparton 3 xilinx FPGA.
DES
- DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
aes
- vhdl implementation of the AES encryption algorithm
aes
- 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
aesencryption
- Aes encryption on Fpga
des_Vhdl
- VHDL & Verilog Synthesizable model of the Data Encryption Standard (DES)
DES
- This is verilog source code for DES(Data Encryption standard) which is used in network security.
Encryption
- AES implementation in VHDL!! Wit LCD controls-AES implementation in VHDL!! Wit LCD controls!!
RC5-VHDL
- RC5 encryption algorithm In VHDL
RC6-block-cipher-using-VHDL
- VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped