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UART_FIFO
- 用VHDL语言实现内置FIFO的UART，并做时序仿真和功能仿真确定正确与否。-Implement a built in FIFO UART using VHDL language, and do functional simulation and timing simulation to determine correct.
usb_packet_fifo
- usb packet fifo VHDL
code
- 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
fifo_srl_uni
- asynchronous fifo in vhdl
uartlvds
- UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
VHDL_RAM_FIFO_ROM
- VHDL代码实现FIFO从ROM中读取数据然后传输到RAM中-VHDL code for FIFO read data ROM to RAM and then transfer