搜索资源列表
fifo.vhd
- This a FIFO in VHDL Code-This is a FIFO in VHDL Code
fifo1k_32
- PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙,精简。 -vhdl fifo sound code
VHDL
- 包括用用VHDL语言编写的DDS,FIFO,交通控制灯,数字电压计,信号发生器的源码,希望能帮到大家-Including the use of VHDL language with the DDS, FIFO, traffic control lights, digital voltage, the signal generator of the source, I hope to help you
FIFO
- 完整的FIFO完整源代码,通过仿真 完整的FIFO完整源代码,通过仿真 -Complete FIFO full source code, through the simulation of the complete FIFO full source code, through the simulation of
VHDLbasicExampleDEVELOPEMENTsoursE
- 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用,介绍如下: Chapter3:schematic和vhdl文件夹,分别是数字钟设计的原理图文件和VHDL程序; Chapter4:multiplier文件夹,串并乘法器设计程序(提示:先编译程序包); Chapter5:sci文件夹,串行通信接口设计程序; Chapter6:watchdog文件夹,看门狗设计程序; Chapter7:taxi文件夹,出租车计价器设计程序; Chapte
fifo
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
fifo
- 这个是我自己写的同步fifo ,供大家参考学习-this the syn-fifo,including testbench
FIFO.tar
- FIFO design VHDL/Verilog design
FIFO
- 先入先出FIFO,用QUARTUS进行仿真-FIFO FIFO, the simulation with QUARTUS
fifo64x8_tb
- Testbench for Xilinx 64x8 FIFO.
fifo
- fifo的代码,经过测试可以使用,很有用处,可以放心使用-a fifo module,the code has been tested and it is usefull
FIFO
- 设计了一个具有双时钟信号,双复位信号的FIFO,用于FPGA中的数据缓冲,RAM的定义是参数型,可以根据自己的需求,修改此参数,完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this
FIFO
- vhdl code for FIFO memory with controler
fifo
- Asynchronous FIFO source code
new_fifo
- 最新的testbench of FIFO ,使用Vmm,VCS,可以大致了解一下VMM的体系-the new fifo VMM testbench
fifouart_latest.tar
- vhdl fifo uart core datasheet
FIFO
- 同步和异步FIFO,VHDL实现。希望对大家有所帮助。-Synchronous and asynchronous FIFO, VHDL implementation. We want to help.
gen_fifo_usb1
- slaver fifo测试模块,分为三个模块,generate产生数据,然后写如fifo.再传如usbslaver fifo-slaver fifo test module consists of three modules, generate production data, and then write as fifo. re-transmission, such as usbslaver fifo
FIFO
- FIFO control in the FPGA-FIFO control in the FPGA