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AnEfficientDouble-FilterHardwareArchitectureforH.2
- 在此提出了一種新穎的硬體結構 實時執行的自適應去塊效應 過濾過程中指定的H.264/AVC視頻編碼 標準。-In this paper,a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented.The deb
H.264decodeVerilog
- 基于FPGA的EDA设计技术，用Verilog硬件设计语言解压缩H.264格式的视频压缩文件。-FPGA-based EDA design, using Verilog hardware design language decompress H.264 video compression format file.
RTP_h_264
- RTP 协议是IETF ( Internet Engineering TaskFo rce) 在RFC1889 中给出的, 是专门为交互式音频、视频、仿真数据等实时媒体应用而设计的轻型传输协议。RTP 被定义为在一对一或一对多的传输情况下工作, 其目的是提供时间信息和实现流同步。RTP 通常使用UDP来传送数据, 但RTP 也可以在TCP 或A TM 等协议下工作.对H.264网络开发有何大帮助- The RTP protocol is given in RFC1889 by IETF (I
nova
- 基于H.264 视频编解码 verilog 基于H.264 视频编解码 verilog-Verilog based on the H.264 video codec based on H.264 video codec Verilog
bluespec-h264_latest.tar
- H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
ML605_RX_H264
- H.264视频压缩硬件语言，基于ＦＰＧＡ的设计语言。非常棒的语言设计-Solution of H.264 video compression hardware design language, based on FPGA language
Exercising-H.264-Video-Compression-IP-Using-Comme
- This book describe about Exercising-H.264-Video-Compression-IP-Using-Commer.
buffer
- Hi iam Ramana a research scholar,doing my phd from sathyabama university. Title: Designa video codec h.264 processor using verilog hdl. i request you to send video codec H.264 on Verilog hdl. regards D Ramana, M.Tech(Ph.D) SATHYABAMA