搜索资源列表
ledyyw
- 用VHDL实现流水灯，配置管脚，并在FPGA板上得到实现-VHDL implementation of water with the lights, configuration pins, and realized in FPGA board
led
- 基于fpga的流水灯仿真以及代码。 包含了整个过程。本人刚刚做过程序在quarter2下仿真成功！ -The water-based light simulation and fpga code. Includes the whole process. I just did the program under emulation in quarter2 success!
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
liushuideng
- 本实验为LED流水灯实验. 本实验为LED流水灯实验.-In this study, experiments for the LED lights running water. This experiment LED water lamp experiment. This experiment LED water lamp experiment.
fft_1024_hdl
- 一个 1024 点 FFT ， 基 4 蝶形运算架构， 5级流水，乒乓内存，有测试环境。-A 1024-point FFT, Radix-4 butterfly structure operation, five water, ping-pong memory, a test environment.
8-led-VHDL
- 8位流水灯程序设计，跑马灯效果显示，里面是VHDL程序。-8 water lamps program design, which is a VHDL program
led_shift
- 本程序代码实现了FPGA中的流水灯功能，可以控制向左还是向右循环点亮发光二极管。-The program code to achieve the water lights in the FPGA, you can control the left or right loop light emitting diode.
8_LigWater
- FPGA，VHDL语言 ：分频1S 8位流水灯，适用于所有FPGA芯片，VHDL源程序-FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !
horse_light4
- 六种花样的流水灯，从左至右，从右至左，中间向两边，两边向中间，跳格闪烁等。verilog语言编写； 并且扩展容易； 有两个状态机构成实现。quartus 9.0和7.1仿真通过。无错误，无警告。-Six kinds of patterns of flowing water lights, from left to right, from right to left, in the middle to both sides, both sides toward the middle, ju
flowingled_top
- 8位流水灯，1个LED灯左右来回循环。2个LED灯左右来回循环-About eight water lights, an LED light back and forth cycle. Cycle back and forth about 2 LED lights
liushun
- 流水灯和跑马灯的程序 已经编译 可以用 是quartus的开发环境-Marquee lights and running water has been the procedure can be used to compile the development environment is quartus
led
- 适用于FPGA初学者,一个流水灯的程序,用VERILOG语言写的.-Applicable to FPGA beginners, a procedure for light water, using the Verilog language.
sopc_led
- 基于EP3C25写的利用FPGA和SOPC做流水灯的Verilog源码-EP3C25 written based on the use of FPGA and SOPC do Verilog source water lights
fir_parall
- 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
xunhuandeng
- 在spartan－3e上利用八个led实现流水灯效果-Spartan-3e in the use of eight led lights to achieve the effect of flowing water
cpld
- CPLD VHDL 数码管程序 流水灯程序 时钟程序 -CPLD VHDL program LED lights water clock procedures procedures CPLD VHDL program LED lights process water clock procedures
The-whole-point-of-time
- 整点报时with流水灯可调时分可调显示星期-The whole point of time with water lights around adjustable adjustable shows a week
liushuideng
- 流水灯程序，１．在ＣＨ－３实验平台上通过ＬＥＤ０～ＬＥＤ７八位ＬＥＤ发光二极管实现流水灯显示，流水效果为LED灯依次亮起，第二个灯亮时第一个熄灭２．用按键切换产生２种流水效果-Process water lights, 1. CH-3 in the experimental platform LED0 ~ LED7 through eight light-emitting diode LED lights show the achievement of water, running water
123
- 基于quartus的，状态机实现流水灯，verilog HDL语言编写-Quartus-based, the state machine to achieve water lights, verilog HDL language
sdram_test
- FPGA开发入门实验，一个SOPC开发实例——流水灯实验，希望对对学者能有所帮助。-Introduction to FPGA development experiment, an example of SOPC development- light water experiment, in the hope that scholars will be helpful.