使用FPGA設計WiMax接收機之OFDM同步硬體電路(內附VHDL code)

VHDL code for convolution encoder for wimax PHY layer. This design also has control to add controlled amount of noise in encoded output.

Wimax矩阵的LDPC编码器，已通过modelsim仿真测试，并前在altera的FPGA板上通过测试,码率5/6，可进入代码内部修改参数，支持2/3,3/4其他2个码率，数据吞吐量为700M-Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m

基于wimax协议的低密度奇偶校验码LDPC的VERILOG实现，亲测可用。-WiMAX protocol based on the low density parity check code VERILOG LDPC implementation, pro test available.