搜索资源列表
LAB2
- 赛灵思新推出的Zynq芯片学习笔记，LED流水灯控制例程，此例程中避开Zynq的PS嵌入式部分，只用PL部分实现逻辑控制。用于新手对Zynq平台的熟悉，让没有接触过FPGA的嵌入式软件工程师友好上手-The Zynq chip Xilinx new study notes, the LED light water control routine, this routine to avoid the Zynq the PS embedded part, only part of the PL lo
ISEPrj
- Xilinx Zynq的PS+PL使用，用PS添加IP核，然后从IP核添加GPIO，并与板上LED相连，实现led的逻辑。注意不能使用helloworld模板。-For the Xilinx Zynq PS+ PL, PS Add IP core, and then add GPIO IP core and connected to the on-board LED, led logic
fpgahdl_xilinx-edk.tar
- xilinx zynq 7000 FPGA demo-xilinx zynq 7000 FPGA demo
the-zynq-book-tutorial-sources
- 一本关于赛灵思Zynq-7000 All Programmable（SoC）的书，是由一群来自英国格拉斯哥斯特拉斯克莱德大学（University of Strathclyde）的作者编撰，并得到了赛灵思的支持，书的作者想打造一本易懂可读的读本，让那些刚刚开始接触Zynq和已经在用Zynq的工程师从中受益，并成为工程师们手头的开发圣经。 本书的配套源代码- A book on the Xilinx Zynq-7000 All Programmable (SoC) book by a gr
xapp1082-zynq-eth
- PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 AP SoC 是学习Vivado 入门文档，源自xilinx，权威易懂 -PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 AP SoC Learning Vivado entr
advconfig
- 在Xilinx Zynq开发板上，通过IIC进行ADV芯片的配置。-In the Xilinx Zynq development board, ADV chip through the IIC configuration.
Tetris_Zedboard
- 俄罗斯方块 ”FPGA实现本项目主要在FPGA上实现了一个经典小游戏“俄罗斯方块”。本项目基本解决方案是，使用Xilinx Zynq系列开发板ZedBoard作为平台，实现主控模块，通过VGA接口来控制屏幕进行显示。-New Tetris
vivado_init
- 该程序是为vivado初始化和配置，并且还包含有相应的说明文档，是初学xilinx vivado的很好的教程，本例程基于zynq系列的MIZ701N处理器进行开发(The program is vivado initialization and configuration, and also contains the corresponding documentation, is a good beginner Xilinx vivado tutorial, this routine based
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
slave
- xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
ug835-vivado-tcl-commands
- Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s
S02_CH02_MIO
- xilinx zynq的mio口测试工程，内容很详细(zynq mio test,about zynq mio pin test,very useful)
zcu102_exp_1
- 给予Xilinx系列zcu102开发板，完成了一个基本的project，实现了PS 端对PL 端的控制，并在PL端自己生成IP，是初学者很好的学习模板。(Xilinx series zcu102 development board, completed a basic project, the PS end to the PL control, and the PL end of the generation of IP, is a good learning template for begi
ug585-Zynq-7000-TRM
- Xilinx Zynq 7000 参考文档(Xilinx Zynq 7000 Reference documents)
i2c
- zynq iic测试,IIC EEPROM接口测试程序，Xilinx参考设计(zynq iic test,The following example shows adding the I2C EEPROM for the ML507 to it's device tree. The value of 0x050 is the I2C address of the EEPROM.)