计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared

实现计数器加法、减法、清零电路。用7448、74ls192实现，可以仿真成功，适用于初学者。-Realization counter addition, subtraction, clear circuit. By 7448,74 ls192 achieve success can be simulated, for beginners.

采用 6 个数码管分别显示小时、分钟和秒的数值； (2) 计时方式可在 12 小时/24 小时之间切换； (3) 通过按键可以对 “时”和 “分”进行校时，同时秒计数器清零。-Using six digital tube display hours, minutes and seconds values (2) the timing mode can be between 12 hours/24 hours switch (3) may be on the when