搜索资源列表
CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
Xilinx_FPGA_DESIGN&CODE
- 完整的FPGA连接图和调试源码，图是DSN格式，但可以直接拖进PROTEL里打开。-integrity of the connection of FPGA and debug source code, the map is DSN format, it can directly dragged into PROTEL Lane open.
FPGA_test_frequency
- 本原码是基于Verilog HDL语言的FPGA原程序，主要用于测频率，特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time higher.
01_GettingStarted
- This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken fro
canbus
- 实现CAN总线的通信，并通过测试验证，用verilog在FPGA上实现-CAN bus communication, and tested to verify that, in the FPGA using verilog
Music_LiangZhu
- FPGA音乐试验，语言：verilog HDL-A FPGA expperientation which can play music Liangzhu，language：verilog HDL
ethernet
- ：提出了一种基于FPGA 实现嵌入式三态(10MB/100MB/1 000MB)以太网的设计方案，分别从硬件和软件方面介绍了使用FPGA 进 行嵌入式系统设计的方法，编写了一个控制系统进行10MB/100MB/1000MB 自切换程序，并在工程中得以实现。-: This paper presents a FPGA-based Embedded Tri-State (10MB/100MB/1 000MB) Ethernet design, from hardware and software,
325
- CPLD下载线制做资料，本人已经根据此制作成功，能够下载，并且有一款很不错的FPGA系统版-CPLD download line information system to do, I have produced based on this success, can be downloaded and there is a very good version of the FPGA system
mcs_51_cpld
- 可以进行单片机与FPGA之间信息的收和发，方便使用-Microcontroller and FPGA can be carried out between the information received and made, user-friendly
CYCLONE2FPGAsch
- 已经验证过的FPGA开发板原理图，想自己设计开发板的可以参考-Has been verified FPGA development board schematics, design and development to its own board can refer to TI
bubble_verilog
- 可综合的基于FPGA实现冒泡排序!资料仅供学习参考，包含tb文件-FPGA-based implementation can be integrated bubble sort! Information for reference purposes only to learn that contains the file tb
DDS
- DDS是在数字电路与实际应用中越来越受重视，无论是在FPGA或者DSP中总能用到它，这里是DDS的一些资料-DDS is in the practical application of digital circuits with more and more attention, both in total FPGA or DSP can be used to it, here is some information on DDS
FPGA-multi-purpose-function-signal
- 基于FPGA的多功能函数信号发生器：基于FPGA实现直接数字频率合成，该函数信号发生器可以实现正弦波、三角波、方波、锯齿波等多种波形输出，输出信号的频率和幅度可调，利用单片机完成整个电路的时序控制、数据处理和实时显示输出。-Based on FPGA multi-purpose function signal generator: based on FPGA realizing direct digital frequency synthesis, this function signal ge
elecfans.com_quargfjc1105
- 学习FPGA仿真软件的书籍，QUARTUS中文教程手册，还是可以收藏一下的。-Books to learn FPGA emulation software, the the QUARTUS Chinese tutorial manual, or can be collected look.
ddsjiangjie
- 一篇关于用FPGA设计DDS的文章，个人觉得还是写得不错的，有着做这个的同学可以下载看看。-An article on the FPGA design of DDS, personally feel that is well written, has to do this students can download to see.
CY3686-Board-Design-Files
- 是驱动CY7C68013A的USB接口系统,可以应用于FPGA、DSP的开发-Driver the CY7C68013A' s USB interface system can be applied to the development of FPGA, DSP
CH376_CODE
- CH376 U盘控制芯片驱动，在FPGA的SOPC平台上调试的，也可以稍加修改就可用在单片机上，串口、SPI、并口三种通信接口选择。-CH376 U disk drive controller chip, the SOPC platform on FPGA debugging can also be slightly modified can be used on single-chip, serial, SPI, three parallel communication interface s
stopwatch
- FPGA程序，verilog HDL语言编写的秒表程序，使用quartus II 13.0 开发，初学verilog HDL的同学可以参考下-FPGA procedures, verilog HDL language stopwatch program, developed using quartus II 13.0, verilog HDL beginner students can refer
EDA
- 基于FPGA的抢答器源代码，能够同时显示4个人的分数，兼备记分牌的作用。-Answer FPGA-based source code that can simultaneously display four individual scores, both the role of the scoreboard.
AT070TN83
- FPGA上AT070TN83的驱动源代码，包括整个工程文件，可直接下载到开发板上-The drive of AT070TN83 on FPGA. Source code and the whole project are included, which can be used to directly write on the board