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大型设计中FPGA的多时钟设计策略
- 大型设计中FPGA的多时钟设计策略,很详细的描述了在FPGA设计中时钟设计的方法-FPGA design large multi-clock design strategy, a very detailed descr iption of the FPGA design clock design method
handover
- FPGA的异步时钟同步处理 从快时钟域到慢时钟域通用的握手信号-The FPGA asynchronous clock common handshake signal from a fast clock domain to a slow clock domain synchronization
fPGA_LED
- FPGA开发板做的一个简单LED驱动，使用Verilog语言实现- This is an example of a simple 32 bit up-counter called simple_counter.v It has a single clock input and a 32-bit output port module simple_count(input clock , output end of module counter
clock
- 利用FPGA来编写程序实现24小时时钟显示-FPGA to program the 24-hour clock display
szz
- verilog HDL 硬件描述语言 FPGA 数字钟的实现 调整时间 闹钟等功能-verilog HDL hardware descr iption language implementations of FPGA digital clock adjustment time alarm clock functions
ISE_lab16
- FPGA/PSOC 电子钟 计时钟 实现方法-FPGA/PSOC electronic clock count clock implementation
clk_gen
- 常见的FPGA 时钟模块代码实例，仅供大家参考-FPGA clock RTL