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ethernet.tar
- 以太网10/100M IP核Verilog源码，可综合。-IP Ethernet 10/100 nuclear Verilog source can be integrated.
CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
FPGA_test_frequency
- 本原码是基于Verilog HDL语言的FPGA原程序，主要用于测频率，特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time higher.
div5
- 简单的VERILOG五分频电路描述，可综合。已经过检验-simple verilog 0.2-frequency circuit descr iption can be integrated. Have been tested
canbus
- 实现CAN总线的通信，并通过测试验证，用verilog在FPGA上实现-CAN bus communication, and tested to verify that, in the FPGA using verilog
Music_LiangZhu
- FPGA音乐试验，语言：verilog HDL-A FPGA expperientation which can play music Liangzhu，language：verilog HDL
RISCCPU
- 简单的CPU设计流程PPT，用于教学目的，可综合的verilog HDL设计。-A simple CPU design process PPT, for teaching purposes, can be integrated verilog HDL design.
f_meter
- Verilog频率计,可以测出1~9999hz的频率，分模块做成顶层文件-Verilog frequency meter can measure 1 ~ 9999hz frequency, sub-module is made of top-level files
SMG_4B
- 采用verilog语言编写，可以成功运行。实现四位数码管的直接显示，把一个二进制的数，输入直接在数码管上显示出十进制的数。-Use verilog language, can be run successfully. Four digital tube displayed directly to a binary number input directly on the digital display the decimal number.
stopwatch
- FPGA程序，verilog HDL语言编写的秒表程序，使用quartus II 13.0 开发，初学verilog HDL的同学可以参考下-FPGA procedures, verilog HDL language stopwatch program, developed using quartus II 13.0, verilog HDL beginner students can refer
NAND01GR3B_VH1
- 存储器verilog仿真代码，可以产生仿真向量对存储器测试。flash存储器选用march算法进行仿真测试。-Memory Verilog simulation code, you can generate simulation vector on the memory test. Flash memory selection of March algorithm simulation test.
FIFO1
- 给出一个位宽16比特，深度为10的异步FIFO的设计，并要求给出空或满的指示信号。要求用Verilog HDL语言设计，并编写测试激励，以及用Modelsim进行功能仿真，验证设计正确性。10个16位的数据 (FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它指的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等。FIFO的深度：THE DEEPTH，它指的是FIFO可以存储多少个N位的数据（如果宽度为N）。如一个8位的FIFO，若深度为8，它可以
verilog_c
- 采用Verilong编写的等精度频率计，调试成功可测频率、周期、占空比、正负脉宽。-Written using Verilog and other precision frequency meter, debugging success can be measured frequency, period, duty cycle, positive and negative pulse widths.
vga
- 直接在quartus 2上运行，然后烧进试验箱，可以播放梁祝，连线就两根，一根连20MHZ，一根连蜂鸣器输入端，另一头连拓展插槽的B01，按键1控制播放、暂停，模式5，可以用点个赞，(Run it directly on quartus 2, and then burn it into the test box. You can play Liang Zhu. There are only two wires, one is 20MHz, one is buzzer input, the oth