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- 储物柜工业控制，包含电子锁控制，身份证ID读取-Lockers industrial controls, including electronic lock control, ID card reading
dpll
- 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis
pll_test
- PLL，即锁相环。是FPGA中的重要资源。由于一个复杂的FPGA系统往往需要多个不同频率，相位的时钟信号。所以，一个FPGA芯片中PLL的数量是衡量FPGA芯片能力的重要指标。FPGA的设计中，时钟系统的FPGA高速的设计极其重要，一个低抖动, 低延迟的系统时钟会增加FPGA设计的成功率。本例程调用Xilinx提供的PLL核来产生不同频率的时钟, 并把其中的一个时钟输出到FPGA外部IO上, 也就是开发板的SMA接口上。(PLL, pll. It's an important resource
锁控板
- 快递柜锁控板的原理图，采用ALTIUM DESIGNER设计(The schematic diagram of the lock control panel of the express cabinet is designed by using ALTIUM DESIGNER)
dpll源程序
- 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the pha
hotel_lock(程序)
- 能够通过LoRa将智能门锁与网关进行通信，可在后台查看门锁状态，实现智能开锁(Through LoRa, the intelligent door lock can communicate with the gateway, and the status of the door lock can be checked in the background to realize the intelligent unlocking.)
BF5821AMXX-应用规格书V5.0_20181224
- 比亚迪BF5812芯片规格书，适合电子自能锁的各种方案。(BYD BF5812 Chip Specification,Suitable for various schemes of electronic self-locking.)