3*3 中值滤波的verilog代码实现，已经调试通过！欢迎提出宝贵意见！-3 * 3 filtering to achieve the verilog code has been adopted debugging! Welcomed the valuable advice!

3x3中值滤波器的FPGA实现(VERILOG),3x3 median filter FPGA implementation (VERILOG)

图像去噪算法的硬件实现，很完整，verilog语言编写的中值滤波，按模块编写，有3乘3模块，计算模块，计数模块-Hardware implementation of image denoising algorithm is very complete, verilog language median filter, according to the module to write, there are three by three module, calculation module, coun