搜索资源列表
xapp904_code
- LCD 控制器件，Writen in vhdl, based on xilinx
xapp485
- XILINX公司关于平板显示\"LVDS接收\"的参考设计,已经过验证非常成熟,用于使用FPGA来做图象增强,Gamma校正,动态背光控制等的设计!
xapp208
- xilinx 基于查找表方法实现的IDCT的verilog源码
svga_timing_generation
- 在640x480,60hz模式下的SVGA显示,显示各种种颜色的竖彩条,时钟频率为50Mhz,在xilinx XC3S400AN的板子上验证过.-In 640x480, 60hz mode SVGA display, showing the various colors of the vertical color, the clock frequency of 50Mhz, in xilinx XC3S400AN verified on the board.
conv5x5_matlab_jtag_XUP_hw_in_loop
- Xilinx MATLAB、SysGen的 图像 DCT工程-Xilinx MATLAB, SysGen image DCT works
FPGA_VGA_displaydoctum
- 使用 FPGA 控制 VGA 显示 相关知识介绍：包括 显示器术语 显示卡术语 VGA 时序设计 色彩原理 显示 源代码 相关测试图片-The use of FPGA control VGA display relevant knowledge, Introduction: terminology, including display graphics card design color theory terminology VGA timing related t
vga_core
- Code VHDL for control VGA FPGA: Xilinx, Altera
zynq_base_trd_14_3
- xilinx的视频处理参考Verilog代码-Video Targeted Reference Design On Xilinx FPGA With Verilog
JPEG-Encoder
- JPEG 编码器的verilog实现，已经在XILINX SPARTAN6上实现并验证。-The JPEG encoder verilog implementation has been implemented in a Xilinx SPARTAN6 and verify.
svga_timing_generation
- 在640x480,60hz模式下的SVGA显示,显示各种种颜色的竖彩条,时钟频率为50Mhz,在xilinx XC3S400AN的板子上验证过.-In 640x480, 60hz mode SVGA display, showing the various colors of the vertical color, the clock frequency of 50Mhz, in xilinx XC3S400AN verified on the board.
xapp208
- xilinx 基于查找表方法实现的IDCT的verilog源码-Xilinx LUT-based method to achieve the IDCT of the Verilog source code
svga_timing_generation
- 在640x480,60hz模式下的SVGA显示,显示各种种颜色的竖彩条,时钟频率为50Mhz,在xilinx XC3S400AN的板子上验证过.-In 640x480, 60hz mode SVGA display, showing the various colors of the vertical color, the clock frequency of 50Mhz, in xilinx XC3S400AN verified on the board.
LogiCORE-IP-Video-Scaler-v4.0
- The Xilinx Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis.
two_ASK
- ask调制在xilinx ise各个版本下的源码和仿真源码-ask the modulation source in the xilinxise
dct2d
- 研究生课程 ： 来源于Xilinx公司，二维DCT变换代码。-Graduate courses: from Xilinx, 2D DCT function implementation verilog code.
lib_dmarc_1d_v1
- xilinx DDR3控制器读数据控制,对读控制器进行了很好的读写封装，可以支持连续和非连续读写。-xilinx DDR3 controller reads the data controller, the read controller package to read and write well, you can support continuous and sequential read and write.
ASK
- AC97控制器，在xilinx的板子上跑的很好，一个ac97的EDK工程，具有很好的实用性-AC97 controller, xilinx board in running well, a ac97 the EDK project, with good usability
bluespec-h264_latest.tar
- 基于xilinx FPGA的H.264视频标准的视频解码编程。-realtime H.264/AVC baseline decoder by xilinx fpga
15010120041_高瑞雪_lab2
- 在本实验中，将使用System Generator for DSP创建一个带乘法器和累加器的12-bit x 8-bit MAC（Multiplier Accumulator），并使用System Generator 的Resource Estimator块来估计资源利用率。 在仿真Simulink中的设计之后，将从该设计中生成VHDL代码和内核，并在Xilinx ISE Foundation开发软件中实现MAC。(Design, construct and verify the specifi
DB46 Xilinx Virtex4-XC4VSX35
- DB46 Xilinx Virtex4-XC4VSX35