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video_compression_systems_I.tar
- 视频压缩算法VHDL实现,值得参考,有8.16.24.32bit模式可选,实现硬件光标-VHDL, is worth considering, a model 8.16.24.32bit optional. hardware cursor
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- VGA彩条信号显示器设计 设计并调试好一个VGA彩条信号发生器,并用EDA实验开发系统(拟采用的实验芯片的型号可选Altera CycloneII系列的 EP2C5T144C8 FPGA。(A VGA color bar signal generator is designed and debugged, and an EDA experimental development system is used (the model of the experimental chip to be use