搜索资源列表
dds(heli).rar
- DDS用verilog 实现，可以实现方波、正弦和三角,DDS using verilog realized, can be square wave, sinusoidal and triangular
H.264Decoder
- H.264解码器，用verilog写成，可以在FPGA上实现baseline的264解码-H.264 decoder, written with verilog, can be achieved in the FPGA on the baseline of 264 decoding
butterfly-verilog
- VHDL的DCT变换.蝶型算法,很好用的,希望能有帮助-The DCT transform VHDL. Butterfly algorithm, very good with the hope that it can be helpful
yavga
- This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable chars
filter_dds_10.29_7.2
- 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
verilogyejingxianshi
- 这是Verilog形成的一个液晶显示的东东，希望可以用到，这个也是经过了各位前辈的运行测试并且成功-This stuff is the Verilog to form a liquid crystal display, and hope can be used after you run a test of the predecessors and success
cbar
- 该verilog 文件输出60hz 1280 *1024分辨率的colorbar，可以直接在vga显示器上显示。-this verilog code generate 60Hz 1280*1024 resolution colorbar,and it can directly displasy on vga monitor.
vga
- verilog语言编写的VGA图像显示,此模块可以直接使用，可以帮助你很好地掌握VGA的驱动-Verilog language VGA image display, the module can be used directly, can help you have a good grasp of the VGA driver
BT656
- BT656资料中文版，可用于视频编解码，支持verilog等工具使用-BT656 information Chinese version can be used for video encoding and decoding, and other tools used to support verilog
vga_stripes_top
- VGA彩条显示,分辨率800*600,使用Verilog显示间隔可设置的红绿条纹,使用工具为xlinx ise.-VGA color display with a resolution of 800* 600, the use of red and green stripes Verilog display interval can be set using tools xlinx ise.
pll
- PLL 锁相环verilog程序 可以直接使用-The PLL can be used directly good use
code-code
- spi，uart等接口的verilog代码和说明文档，能帮助大家了解总线的功能。-spi, uart verilog code and documentation, such as interfaces, can help you understand the function of the bus.
dct2d
- 2D-DCT, 二维离散余弦变换模型。能够通过Synplify DSP生成Verilog代码 -2D-DCT model. This simulink model can generate RTL code via Synplify DSP.
DCT
- 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
camera_model
- 原创的cmos sensor摄像头的verilog模型，可作为camera控制接口的仿真和验证。-Original verilog model cmos sensor camera can be used as simulation and verification camera control interface.
7_to_1-LVDS-dispaly-from-FLASH
- 该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕-The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and sup
base2-8fft-verilog
- 一个实现基2 8点傅里叶变换的verilog程序-A multi-point Fourier transform matlab program, you can see the real and imaginary parts of processed data.
sort
- 实现图像的滤波，使用VERILOG语言，自己是在FPGA中实现的，其他的也可参考(To achieve image filtering, the use of VERILOG language, and they are implemented in FPGA, the other can also refer to)
main_naive.cpp
- 完成滤波功能, 可以编译,转化为verlog代码.(This code complete filter funciton. It can be used and turned to Verilog code)