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该代码是用VHDL编写的用以实现5/3无损小波变换。压缩包内附有详细的说明。-the VHDL code is used to prepare for the realization of the 5 / 3 wavelet transform prejudice. Compression packet containing a detailed explanation.
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9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述：-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code:
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9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述：-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code:
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