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cbar
- 该verilog 文件输出60hz 1280 *1024分辨率的colorbar，可以直接在vga显示器上显示。-this verilog code generate 60Hz 1280*1024 resolution colorbar,and it can directly displasy on vga monitor.
eDP
- eDP接口TFT-LCD显示驱动原码（verilog+c）-eDP Interface TFT-LCD display driver source code (verilog+c)
hdmiadvi-Demo
- HDMI & DVI interface reference verilog and VHDL code
pal
- FPGA产生PAL-D的VHDL和Verilog代码。-The code is used to generate the sequence of PAL with FPGA in VHDL and Verilog
7_to_1-LVDS-dispaly-from-FLASH
- 该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕-The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and sup
TFT_LCD
- 产生逻辑画面的R/G/B/黑/白等画面的完整verilog源码，通过修改宏定义方便修改成支持各种尺寸的LCD驱动，本源码为RGB格式输出接口-Complete verilog source code generation logic screen R/G/B/black/white screen, etc., by modifying the macro definition modified to support a variety of convenient size LCD driver,