基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run

实现CAN总线协议，完成数据在总线上高效、稳定的传输功能-Realize CANbus protocol, data on the bus are efficiently and stablely atransferred function