搜索资源列表
riscdesign
- 一个非常简单的cpu设计的原代码,是用verilog编写的-a very simple cpu design of the original code, was prepared by the Verilog
dft
- verilog语言实在点变换DFT源代码,可以配合软核或者其他CPU进行综合FFT变换,也可以单独使用生成module!-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!