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tuxiangtiqu
- 自己做用FPGA实现VGA显示时，图像提取信息的matlab程序-FPGA realization of their own with VGA display, the image information extraction matlab program! ! !
FPGA_AVR_timer
- 实现FPGA和AVR之间的简单通信，有FPGA产生时间信号，AVR单片进行出来 和显示-Between the FPGA and AVR to achieve simple communications, and have time FPGA signal, AVR-chip to come out and display
l602display
- 1602显示单片机与FPGA的通信！实现数字钟的功能！仅供参考！望大家多多指教-desplay1602
09_uart2
- PC机上开串口调试助手，发送一个字符到开发板（中间通过串口线相连） FPGA收到字符后，回发给PC机上，在串口助手上显示 -On the PC, open the serial port on a PC debugging assistant to send a character to the development board (in the middle connected by serial cable) FPGA received character back to the s
12_lcd12864
- 本实验是用LCD12864显示英文 显示 Our FPGA EDA NIOS II SOPC FPGA-This experiment is with LCD12864 show displayed in English Our FPGA EDA NIOS II SOPC FPGA
frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
Display-a-heart-shape-code
- Display a heart shape code点阵显示爱心形的FPGA Verilog 代码-Display a heart shape code
Key-and-digital-tube-display
- 按键和数码管显示，FPGA的verilog代码-Key and digital tube display
Multiplier-digital-tube-display
- 乘法器数码管显示，FPGA的verilog代码-Multiplier digital tube display
Division-of-digital-tube-display
- 除法器数码管显示，FPGA的verilog代码-Division of digital tube display
Adder-digital-tube-display
- 加法器数码管显示，FPGA的verilog代码-Adder digital tube display