搜索资源列表
13lab03
- 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（3）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (3)
CORDIC_FLOAT
- 这是一个数值计算算法在FPGA中实现的东东。包括CORDIC算法的详细资料还有float型数的详细论述，可供参考。-This is a numerical algorithms in FPGA achieve saucepan. CORDIC algorithm include detailed information is the number of float-type discussed in detail for reference.
canbus(FPGA)
- 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run
cossincordic.rar
- CORDIC算法的Matlab模拟，为了验证FPGA实现CORDIC算法的时间特性优于软件，用Matlab实现了一个计算sin, cos的CORDIC算法,Matlab simulation CORDIC algorithm, in order to verify the FPGA to achieve the time characteristics of CORDIC algorithm is superior to software, using Matlab calculated to
20100407
- 用MATLAB仿真的数字下变频程序，变频，滤波未用matlab函数，而是用代码完成，便于移到DSP或FPGA上。供参考。-Using MATLAB simulation of digital down conversion process, conversion, filtering is not used matlab functions, but with code completion, easier to move on a DSP or FPGA. For reference.
dynamic_co-operation_cordic_fpga
- 一篇关于使用cordic实现动态配置以提高FPGA的整体性能的高效算法具体详解，很实用哦-On the use of CORDIC realization of a dynamic configuration to improve the overall performance of FPGA-specific high-performance algorithms explain, it is practical Oh
DDSF
- A direct digital frequency synthesizer based on cordic algorithm implemtnted with FPGA
ResearchandImplicaofAutochargingEquipmentBasedonDS
- ：介绍了一种利用DSP控制的大容量蓄电池自动充电装置的设计。采用高频开关电源技术，给出了基于数 字信号处理器TMS320LF2407的充电装置控制系统的软、硬件设计。借助Matlab中的Simulink仿真工具，采用 在线模糊自整定技术对充电装置控制系统进行仿真，并将仿真结果应用于DSP控制器中，实现对Fuzzy-PID控 制的Kp、Ki、Kd参数的在线自整定，使充电方式能较好的模拟最佳充电曲线，达到理想效果。理论分析和试验都 表明，该充电装置能够有效地提高蓄电池的充电效率，加快
filter
- 这是基于MATLAB下的XILINX的FPGA的FIR滤波器的模型设计文件-This is a MATLAB-based FPGA of the XILINX Model of the FIR filter design documents
157
- Encryption algorithms are becoming more necessary to ensure data is securely transmitted over insecure communication channels. FOX is a recently developed algorithm and its structure is based on the already proven IDEA (International Data E
fenyan
- 这是一个关于fpga不同语法进行分频产生延时多少的简易分频测试程序，可以用来检查不同分频语法所用延时多少及性能测试-This is a different syntax on the fpga delay resulting sub-band frequency of the number of simple sub-test procedure can be used to check the syntax of the different sub-band number used in de
MatlabFIRFPGA
- 这是篇关于matlab环境下的数字滤波器的论文，基于Matlab的FIR滤波器设计及FPGA实现-This is a chapter on the environment matlab digital filter paper, based on Matlab for FIR filter design and FPGA implementation
divider
- 流水型除法器，经过FPGA平台验证。宽度可以任意修改，提供计算完毕信号。-Water-type divider, after a FPGA platform validation. Width can be modified to provide the calculation is completed the signal.
JPEG-LS
- 基于改进JPEG-LS算法的遥感图像近无损压缩专利，由航天五院508所申报，很详细的介绍了算法和fpga的实现-Improved JPEG-LS algorithm near lossless compression patent, the space the five branches of 508 reporting, a detailed explanation of the algorithm and implementation fpga
yunchengxu
- 内附几十种小程序，有状态机、比较器、波形发生器、乘法器、加法器、步进电机控制器等，希望大家能用的上。-Containing dozens of small programs, for reference，This is about FPGA,a tool ,we can study,but in ourselves.
nlpf
- This simple Matlab function simulates a innovative algorithm for narrow band interference mitigation for wireless communications, esp for satellite comm. The algorithm looks similar to LMS, but error is non-linearly transformed. It works well and a
sinwave
- 生成FPGA编程中rom初始化需要的.mif文件。生成的为1/4周期正弦波数据。宽度为8，深度为1024-Generate FPGA programming rom initialization required. Mif file. Generated 1/4 cycle sine wave data. Width is 8, a depth of 1024
squarewave
- 生成FPGA编程中rom初始化需要的.mif文件。生成的为1个周期方波波数据。宽度为8，深度为1024-Generate FPGA programming rom initialization required. Mif file. Generated for a cycle square wave data. Width is 8, a depth of 1024
shuangjixingbo
- 生成FPGA编程中ROM初始化所需要的.MIF文件。该程序生成的是双极性波的波形数据。生成的数据宽度为8，深度是1024。-ROM generation FPGA programming needed to initialize. MIF file. The program is a bipolar wave generated by the waveform data. Generated data width is 8, the depth is 1024.
Display-a-heart-shape-code
- Display a heart shape code点阵显示爱心形的FPGA Verilog 代码-Display a heart shape code