这是基于MATLAB下的XILINX的FPGA的FIR滤波器的模型设计文件-This is a MATLAB-based FPGA of the XILINX Model of the FIR filter design documents

jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL

采用MATLAB实现定点的FFT运算，但是仿真硬件结构的IP核调用以及误差产生模式，用于仿真FPGA实现FFT运算的效果和误差来源。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, the fixed-point implementation using MATLAB FFT operation, but the hardware structure of