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81i_radix2_xfft1024_v3_2
- xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
pc_cfr_v2_0_msim_r2_0
- Xilinx公司pc_cfr IP核的MatLab仿真-matlab simulation model of pc_cfr ip core of xilinx
tri_mode_eth_mac
- The LogiCORE™ IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mbps Ethernet MAC, 1 Gbps Ethernet MAC and the 10/100 Mbps Ethernet MAC IP core. All cores support half-duplex and full-duplex operatio
1xy7z.ZIP
- 基于SOPC系统的JPEG解码IP核设计SOPC system based on JPEG decoding IP core design-SOPC system based on JPEG decoding IP core design
fpga-jpeg-Verilog
- jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL
fft_ly
- 采用MATLAB实现定点的FFT运算，但是仿真硬件结构的IP核调用以及误差产生模式，用于仿真FPGA实现FFT运算的效果和误差来源。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, the fixed-point implementation using MATLAB FFT operation, but the hardware structure of
CONVERT
- This scr iptconvert a image to coef values for ip core block ram generator xilinx