基于FPGA的usb程序，采用VHDL语言编写。 开发环境为ISE或者MAXPLUS2。-FPGA-based usb procedures, using VHDL language. Development Environment for the ISE or MAXPLUS2.

无线通信FPGA设计的所有源码，具有良好的使用价值-verilog matlab ISE

其中详细的介绍了matlab中的simulink仿真时ise联合仿真时所用到的system generator的用法，对做fpga很有帮助哦-Described in detail the usage of the system generator used in the joint simulation in matlab simulink simulation ise to do fpga helpful.

This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p