This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both

matlab下设计的pll锁相环，适用于电网电压锁相，不平衡锁相效果还没测试(pll phase lock with matlab simulink, haven't been tested for unbalanced situation)