搜索资源列表
jpeg_encoder
- 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining ci
jpeg_yuce
- 预测编码dpcm 的verilog代码，此文件为V文件-predictive coding dpcm verilog code of this file documents for V
jpeg压缩中的DCT蝶型算法verilog代码
- jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
GF_binomial
- 為一個可處理多項式乘法的verilog code
BCD2BIN8.rar
- BCD转BIN算法，BCD码转二进制数据。,BCD to BIN algorithm, BCD code to binary data.
fft
- fft代码,采用蝶形算法,包括C,matlab和verilog代码-fft code, using butterfly algorithm, including C, matlab and Verilog code
dft
- verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!
RFC_1622_CRC16_m
- RFC1662 CRC-16 table generation and CRC checking. Implemented in embedded matlab with scr ipt to test and enable c/c++ code generation. Useful fo check against VHDL/Verilog and other embedded systems to help generate test vectors.
hdl
- 对lvds的结构用verilog和vhdl代码进行了详细的描述-The structure of the lvds with verilog and vhdl code described in detail
fir_filter_verilog
- FIR filter verilog project
LIP6492CORE_zigzag
- Compression ZingZang RTL Verilog source code
fsm_example2_TB
- verilog code for if defined
DCTPROGRAM.ZIP
- it is verilog code for two dimentional dct
16bit-CLA
- a 16 bit carry look ahead adder verilog code
Easy-convolution-Verilog-file
- convolution code for beginers in the field of communication
BCH[31-16]-with-BPSK-MFSK
- comperation of performance of BCH [31 16] code with BPSK and MFSK
AWSEQ_RAM_RW_A_DFF
- Verilog AWSEQ RAM DFF Verilog code
wireless
- 无线通信FPGA设计Matlab Verilog代码-Wireless FPGA design Matlab Verilog code
add16
- designing of 16 bit adder using 4 bit adder using verilog code
原边反馈反激变换器开环verilog代码
- 原边反馈反激变换器开环verilog代码(The primary side feedback flyback converter open-loop Verilog code)