基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,

16位除以8位除法器，Verilog HDL语言-16 divided by 8 divider, Verilog HDL language

从原理到实现的循环除法器的Verilog代码-Circular divider from the principle to the implementation of the Verilog code

this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.