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RFC_1622_CRC16_m
- RFC1662 CRC-16 table generation and CRC checking. Implemented in embedded matlab with scr ipt to test and enable c/c++ code generation. Useful fo check against VHDL/Verilog and other embedded systems to help generate test vectors.
fft
- 16 point 4 radix fft vhdl
Cordic
- 用verilog写的Cordic运算模块，迭代次数为16次。-Cordic Module Writing With Verilog。
95637012Multiplier
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multiplier.-- the design makes use of
divider
- 16位定点无符号数除法器，除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成-Unsigned 16-bit fixed-point divider, divisor, dividend by 16-bit integer and 16 fractional bits, commercial 32-bit integer and 16 by the decimal form, the remainder from 32 fractional bits
example7--21.10.2011
- full adder subtractor 16 bit for vhdl
16x16multiplier
- Design, simulate and synthesize a 16-bit integer multiplier using only one 4-bit adder. This 4-bit adder is to be made with four 1-bit adders as components. The coding is in VHDL.-Design, simulate and synthesize a 16-bit integer multiplier using only