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canbus(FPGA)
- 基于FPGA的can 总线设计,采用verilog语言编写。在FPGA的开发环境下,新建一个工程,然后将本文件中的各个源代码添加进工程里,即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run
CompressionLZ77-LZ78-HUF-ARI-LZW-RLE
- 非常全面的无损压缩算法集合,编译通过,可以运行!-Very comprehensive collection of lossless compression algorithm, compiles, you can run!
inter_prediction(verilog)
- H.264算法中的帧间估计部分的设计,能够实时处理720x576图像。-The inter predictions part design of H.264,which can process 720x576 image.
iqit(verilog)
- H.264算法中的反变换反量化部分的设计,能够实时处理720x576图像。-The IQIT part of H.264, which can process 720x576 image.
frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包,解压后可直接下载到DE2板上,其中频率输入端是系统自带27M时钟D13用于测试,如果想要应用于别的开发板,可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
verilogPHDL-classic-tutorial
- verilog+HDL 金典教程,可以为初学者带来很大的方便,便于学习与理解-verilog+HDL Golden tutorial, you can bring great convenience for beginners, easy to learn and understand
jpegencode_latest.tar
- jpeg压缩编码电路,verilog编写,可以综合。-jpeg compression coding circuit, verilog writing can be integrated.
CAVLE-h264
- 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块(Verilog和VHDL两个版本),包含有仿真的testbench测试文件,综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used d
test_5.0_tetris
- 基于Vivado实验平台,用Verilog语言编写的俄罗斯方块,可以在FPGA硬件上上下载运行(Based on the Vivado platform, the Tetris block written in the Verilog language can be downloaded on the FPGA hardware.)