Verilog语言求解均方根的近似方法，用MATLAB仿真实现，思想可移植到FPGA中-Verilog language rms approximate solving method, using MATLAB simulation, ideas can be transplanted into the FPGA

介绍了一种简化的SVD分解算法，这个算法已在MATLAB上验证，可以用于fpga上实现-ntroduces a simplified SVD decomposition algorithm, this algorithm has been validated in MATLAB can be used to achieve the fpga