搜索资源列表
riscdesign
- 一个非常简单的cpu设计的原代码,是用verilog编写的-a very simple cpu design of the original code, was prepared by the Verilog
GF_binomial
- 為一個可處理多項式乘法的verilog code
BCD2BIN8.rar
- BCD转BIN算法，BCD码转二进制数据。,BCD to BIN algorithm, BCD code to binary data.
fir_filter_verilog
- FIR filter verilog project
AWSEQ_RAM_RW_A_DFF
- Verilog AWSEQ RAM DFF Verilog code
two_dimensional_fast_hartley_transform_latest.tar
- RTL Verilog code to perform Two Dimensional Fast Hartley Transform (2D-FHT) for 8x8 points. Presented algorithm is FHT with decimation in frequency domain.
loschoros
- SPI master verilog code
xunfachufaqi
- 从原理到实现的循环除法器的Verilog代码-Circular divider from the principle to the implementation of the Verilog code
day8_alu_design
- this verilog code for designing ALU in fpga.-this is verilog code for designing ALU in fpga.
Reed_Solomon
- 这个verilog代码的例子实现的是某种情况下的错误的纠正 error correction的功能-Examples of this verilog code error correction is implemented in the case of some error correction function