搜索资源列表
PN_Generator.rar
- 用Verilog编写的一个简单的产生伪随机序列的代码（m序列），比较实用。,Verilog prepared with the emergence of a simple pseudo-random code sequence (m sequence), more practical.
ddc.rar
- 数字下变频器的matlab实现，一定的设计指标，可以用来知道vhdl程序设计,Digital Down Converter for matlab realized, certain design specifications that can be used to know VHDL Programming
fft
- fft代码,采用蝶形算法,包括C,matlab和verilog代码-fft code, using butterfly algorithm, including C, matlab and Verilog code
RFC_1622_CRC16_m
- RFC1662 CRC-16 table generation and CRC checking. Implemented in embedded matlab with scr ipt to test and enable c/c++ code generation. Useful fo check against VHDL/Verilog and other embedded systems to help generate test vectors.
FILTER
- 数字滤波器设计实例，里面包含VERILOG语言和MATLAB语言写的代码。-Digital filter design example, which contains the VERILOG language and MATLAB language to write code.
16bit-CLA
- a 16 bit carry look ahead adder verilog code
Easy-convolution-Verilog-file
- convolution code for beginers in the field of communication
BCH[31-16]-with-BPSK-MFSK
- comperation of performance of BCH [31 16] code with BPSK and MFSK
wireless
- 无线通信FPGA设计Matlab Verilog代码-Wireless FPGA design Matlab Verilog code
add16
- designing of 16 bit adder using 4 bit adder using verilog code
dac
- DAC CODE数据转换器设计里面将数字代码如何转换为模拟，与输入进行比较-VERILOG CODE
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
verilog
- CHANNEL ESTIMATION CODE
原边反馈反激变换器开环verilog代码
- 原边反馈反激变换器开环verilog代码(The primary side feedback flyback converter open-loop Verilog code)
e60a9bd4-ef5c-4c89-bfb3-9da40d5e4aba
- 低密度校验码 ，很好用的代码，功能已经实现编码和译码(Low density parity check code, very good code, the function has been achieved encoding and decoding)
源码 基于XILINX FPGA的ofdm通信系统基带设计
- verilog 源码 基于XILINX FPGA的ofdm通信系统基带设计(Experiment of digital signal processing: parallel filtering experiment code. I hope it will help.)
CICFilter
- 一个CIC滤波器的源代码，基于verilog HDL语言(The source code of a CIC filter is based on Verilog HDL language.)
数字滤波器的MATLAB与FPGA实现例程代码567
- 数字滤波器的MATLAB与FPGA实现——杜勇(配套光盘) 程序源码，配合电子书使用可以很好的学习数字滤波器的MATLAB与FPGA实现，完整代码，仿真良好，第5、6、7章((MATLAB and FPGA implementation of digital filter -- Du Yong (supporting CD-ROM) program source code, can learn matlab and FPGA implementation of digital filter we
Chapter_9
- 数字滤波器的MATLAB与FPGA实现——杜勇(配套光盘) 程序源码，配合电子书使用可以很好的学习数字滤波器的MATLAB与FPGA实现，完整代码，仿真良好，第9章((MATLAB and FPGA implementation of digital filter -- Du Yong (supporting CD-ROM) program source code, can learn matlab and FPGA implementation of digital filter well w