RFC1662 CRC-16 table generation and CRC checking. Implemented in embedded matlab with scr ipt to test and enable c/c++ code generation. Useful fo check against VHDL/Verilog and other embedded systems to help generate test vectors.

Design, simulate and synthesize a 16-bit integer multiplier using only one 4-bit adder. This 4-bit adder is to be made with four 1-bit adders as components. The coding is in VHDL.-Design, simulate and synthesize a 16-bit integer multiplier using only