BOI version of Steiner tree construction, practical and popular for manhattan VLSI routing, generate a Steiner minimum tree for given set of terminals in a layout plane-BOI version of Steiner tree construction, practical and popular for manhattan VLS

Construct buffered routing tree for VLSI interconnects in a Manhanttan layout plane for a given set of terminals, guarantee polarity of the terminals agree with each other

FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea of gate and standard cell designs, scales well into million gate designs-FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea