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saa7111_2
- 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制，将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A / D chip to control the collection, image data are stored in synchronous FIFO - AL422B
fifo
- 实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能，简单易懂，并带有相应的测试文件-Fifo realize the basic functions. Be able to use the Verilog implementation of the synchronous data FIFO functions, easy to understand, with the corresponding test file
asynFifo
- 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
fifo
- 一个先进先出的内存，使用一个同步时钟产生各种不同尺寸的高速缓冲-a first-in first out memory, uses a synchronising clock generics allow fifos of different sizes to be instantiated
FIFO
- FIFO以及跨时钟域的同步问题。 FIFO有分离的地址总线和用以读写数据的数据通道，以及指示堆栈状态（满、将满等）的状态线。-FIFO as well as cross-clock domain synchronization. FIFO have separate address bus and read and write data to the data channel, as well as the instructions state stack (full, will be fu
fifo_syn
- 同步fifo并有详细的文档说明，希望对大家有帮助-Synchronous fifo and detailed documentation, we want to help
fifo_ram
- 同步fifo， 基于FPGA的VHDL编程，已调试。-fifo-ram
fifo_internet
- 一个同步FIFO的例子。通过读写指针控制FIFO的空和满-A synchronous FIFO example through reading and writing pointer control FIFO empty and full
fifo
- 同步fifo vhdl语言 16乘以8 能够进行仿真- 16 synchronous fifo vhdl language can be simulated by 8
DBfifo
- 同步FIFO设计源代码，带有复位信号的同步FIFO设计，能够在同一个时钟域范围内写入读出数据，从而做到传递数据的功效。-Synchronous FIFO design source code, synchronous FIFO design with a reset signal, can write and read data in the same clock domain range, so do efficacy data transfer.