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fifo
- 基于verilog的异步fifo设计，仿真效果良好-asynchronous fifo based on zhe verilog language
FIFO
- 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
asynFifo
- 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
Chapter-9
- 9.1 异步FIFO设计实例 9.2 DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
Asynchronous-FIFO-
- 异步FIFO是一种先进先出电路，可以有效解决异步时钟之间的数据传递。通过分析异步FIFO设计中的难点，以降低电路中亚稳态出现的概率为主要目的，大大提高工作频率和资源利用率。-Asynchronous FIFO is an advanced circuit that can effectively solve the data transfer between asynchronous clock. Through the analysis of the difficulties in async