搜索资源列表
fifo_ver_131
- fifo verilog hdl 源程序-fifo verilog hdl source
FIFO
- 一个异步的FIFO的VERILOG程序,有测试程序
FIFO
- fifo.v verilog实现的先进先出存储器
yibu_FIFO_design
- 异步FIFO实例，精通verilog hdl中的例子，供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning
fifo
- 基于verilog的异步fifo设计，仿真效果良好-asynchronous fifo based on zhe verilog language
FIFO
- 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
fifo
- 先进先出缓存器的verilog设计与实现-design of fifo(first in first out)
fifo
- 实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能，简单易懂，并带有相应的测试文件-Fifo realize the basic functions. Be able to use the Verilog implementation of the synchronous data FIFO functions, easy to understand, with the corresponding test file
cfifo_ptrs_binary
- system verilog fifo env
VERILOGFIFO
- FIFO的verilog描述-Verilog descr iption of the FIFO
FIFO_IN_VERILOG
- 基于Verilog的fifo的实现源码和测试文件-Fifo-based realization of the Verilog source code and test file
FIFO
- 利用Verilog实现了一个FIFO，包含几个模块文件，适合初学Verilog的朋友，含测试代码。-Verilog achieved using a FIFO, a document contains several modules, suitable for novice Verilog friends, including test code.
VHDLFIFO
- 用Verilog 写一个8x16 的FIFO，完成先入先出的功能，并且在FIFO读空时输出EMPTY 有效信号，读指针RP 不再移动；FIFO 写满时输出FULL 有效信号，并且即使WR 有效也 不再向存储单元中写入数据(写指针WP 不再移动)。 -NO
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
FIFO
- 是用verilog HDL写的基于FIFO的串口发送机的设计，很详细的代码，很值得学习，已经验证通过-With verilog HDL based on FIFO serial transmitter design, write code, it is worth learning, has been verified by.
fifo
- 基于Verilog的fifo源码，经验证，有效，实用-very good
sync_FIFO
- asynchronous fifo verilog code
SDRAM-and-FIFO-for-DE1-SoC-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.