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FPGA_fenpin
- 分频器 FPGＡ程序设计 二分频 对硬件设计有很大用处 -Divider FPGA design process for two minutes frequency hardware design, very useful
cpld
- 一个好用的整数分频电路 保证你喜欢 能够实现对任意整数的分频电路设计-a handy integer frequency divider circuit assures you like to be able to achieve arbitrary integer frequency circuit design
frequency
- frequency divider circuit divides the input frequency (clk) by various factors
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
20080108103305384
- 本系统是采用EDA技术设计的一个简易的八音符电子琴和音乐发生器，该系统基于计算机中时钟分频器的原理，采用自顶向下的设计方法来实现，它可以通过按键输入来控制音响。系统由乐曲自动演奏模块、乐器演示模块琴/乐功能选择模块、音调发生模块和数控分频模块五个部分组成。系统实现是用硬件描述语言VHDL按模块化方式进行设计，然后进行编程、时序仿真、整合。本系统功能比较齐全，有一定的使用价值.-The system is designed using EDA technology with a simple ei
8fen
- 8分频器的VHDL源码，绝对正确，并且可根据本代码推导出各个2的幂数的分频器的编写原理。-FDCT Frequency Divider by VHDL .
Simplified-2-frequency-divider
- 用verilog语言编写的两个2分频小程序，通过了验证。-Two small written in Verilog language frequency divider applet, passes validation.
beep-sing(VHDL)
- 向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调 该实验通过设计一个状态机和分频 器使蜂鸣器发出"多来咪发梭拉西多"的音调。 -Sent to the buzzer frequency square wave of the experiment through the design of a state machine and divider buzzer sounded " more than a microphone Fat shuttle Rasi multi to
UniversalDIV
- UNIVERSAL FREQUENCY DIVIDER pin sets for Digilent Basys 2 (Spartan3E-250) fout = (K(0)*100+ K(1)*10 + K(2))*10K(3)
half_clk
- 此为用Verilog编写的1/2分频器，用以将信号的频率变为原来的2被-This is written using Verilog 1/2 frequency divider for the frequency of the signal into the original two were
clock_speed
- fpga分频器设计。将高频时钟信号任意分频-fpga crossover design. The high frequency clock signal any divider
div_freq
- 分频器，把一个特定的频率进行分频，从而得到自己想要的频率-Frequency divider, a specific frequency divider, you want to get the frequency