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clock
- 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!
clock
- 很好的多功能数字钟的HDL代码不可多得的哦-Good multi-function digital clock of the HDL code rare Oh
as1
- Verilong HDL是最frequenctly使用的硬件描述语言，因为它的简单和方便的属性之一。这当然AIMES设计一个数字时钟，配备4段显示，秒表和时间设定使用这种语言，甚至一些额外的功能，fundamatal。 DE1板设计时钟的实施贡献-Verilong HDL is one of the most frequenctly used hardware descr iption language because of its simple and convenient propertie
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
OV7725_i2c_timing_ctrl
- iic接口verilog HDL代码，经过测试验证，在OV7725控制接口上验证- //i2c interface output i2c_sclk, //i2c clock inout i2c_sdat, //i2c data for bidirection //user interface input [7:0] i2c_config_size, //i2c config data counte output reg [7:0] i2c