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ref-ddr-sdram-vhdl
- 本程序是DDR SDRAM控制器的VHDL程序,由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
sram
- sram操作vhdl源程序,内有sdram模型,控制器设计,及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
ddrsrdram
- ddr sdram information
DDRSDRAM
- DDR SDRAM设计及调试经验总结.pdf
ddr2_device_operation_timing_diagram_may_07_1
- DDR2时序规范,DDR· DDR2时序规范,DDR·-DDR2 timing norms, DDR DDR2 timing norms, DDR
DDR+SDRAM控制器verilog代码及中文说明文档
- DDR SDRAM控制器代码,不可多得的源代码。内附详细说明文档。
Chapter-9
- 9.1 异步FIFO设计实例 9.2 DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
ddr_sdram
- this document explain de function of ddr sdram controller