昨天在论坛上看到有人帖出了他写的并串转换VHDL代码，但是他自己说有问题，但是不知道怎么改。我大概看了一下，发现思路还是比较乱的。于是就写下了我自己的并串转换代码。-yesterday at the forum see someone points out his writing and string conversion VHDL code, But he said there are problems, but does not know how reform. I probably wat

spi源码，是verliog的，有需要的可依参考进行设计自己的工程，后续有需要还有一个使用说明附上-spi-source is the verliog, reference may need to design their own projects, there is a need to have a follow-up instructions attached

实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.